Clock distribution technology is currently a hot topic in the microprocessor design industry because microprocessor performance is typically limited by the accuracy and frequency of the clock signal. Any error in jitter or skew of the clock signal must be compensated for by increasing the clock period, however, increases in clock period typically reduce microprocessor operating frequency and performance. Accordingly, accurate clocking circuits are desirable.
With the widely used H-tree clock distribution network illustrated by FIG. 1, clock skew can be minimized by carefully matching the wiring delays across an integrated circuit (IC). However, H-tree clock distribution networks are typically limited to only a single clock phase. Novel clock circuit structures designed to further improve microprocessor clocking are continually emerging, but thus far circuits that incorporate both multiphase signal generation and efficient distribution have yet to be satisfactorily developed. It is advantageous to utilize multiphase clocks in many designs because clock cycle time can be reduced by breaking up critical paths into smaller delays with greater latency. Also, the availability of multiple phases aids creative circuit designers in producing faster logic circuits and latches. Another disadvantage of feed-forward clock distribution circuits such as the binary H-tree network of FIG. 1 is that clock skew increases with chip size. As chip sizes increase, the wiring delay and the number of synchronous active devices (e.g., latches) increase and result in greater load capacitance and correspondingly higher clock skew.
Thus, clocking circuits are needed which are more suitable for large integrated circuit chips and provide reduced clock skew and jitter. Moreover, clocking circuits are needed which provide for the efficient generation and distribution of multiphase clock signals to synchronous active devices on an integrated circuit chip.